1.0 Introduction
In recent years, for the sake of maximizing profits, suppliers of single-crystal silicon wafers pursue a good process as long as single crystals do not fall. The dislocation-free pull crystal process requires that the seed crystal be cut with no dislocation pull crystals. In the pulling process, the length of the next seeding neck should be larger than one ingot diameter in order to displace the dislocations before putting the shoulders. Now, the length of the neck 120-140mm is completely lower than the 6-inch diameter 150mm single crystal. In addition, when the end of the single crystal to ensure that the end of the pot is about 10% of the amount of material, and now single crystal suppliers can not wait to pull all the finished material. Little did they know that when they tried to remove a little of the contents of the pan, they had caused the melt in the pan to become too cold. Once the material was too cold, it would fall out. It looks like it has been completely closed, but it has actually fallen out. This way, a single crystal of a diameter is already a dislocation. Vendors have passed these bits of dislocation completely to users.
2.0 Black Patches
Electro-luminescent EL (Electroluminescence) photographs of black and black patches reflect the absence of 1150 nm infrared light emitted under the condition of power, so the infrared photographs reflect black hearts and dark spots. The luminescence phenomenon is related to the minority carrier concentration of the silicon substrate.
Figure 1 Black chip (left) and black patch (right)
The electrical performance test of the components is shown in the figure below. As can be seen from the figure, the component short-circuit current Isc (4.588A) and the maximum power Pmax (143.028W) are significantly lower; such a normal component short-circuit current Isc is generally 5.2A, and the maximum power Pmax is generally 175W or more. Explain that there are a large number of inefficient solar cells in the assembly, resulting in a serious drop in the power of the assembly.
Figure 2 Component Electrical Performance and EL Testing
Electroluminescent EL tests were performed on the cells as shown in Figures 3 and 4 below. Its black heart and dark spots are as seen in the EL test.
Figure 3 Sample 1EL Test Figure 4 Sample 2EL Test
Lighting conditions The battery electrical performance tests are shown in Table 1.
Table 1 Light conditions battery electrical performance test
The two cell efficiencies were 11.06% and 13.99%, respectively, and the Isc were 4.73A and 4.62A, respectively, both of which were significantly lower. The efficiency of such normal cells is generally about 17.5%, and Isc is about 5.3A.
Battery light-induced current density (LBIC Current) tests are shown in Figures 5 and 6.
Figure 5 Sample 1 LBIC Current Test Figure 6 Sample 2 LBIC Current Test
Then, after the battery passes through the SiN film, the positive and negative electrodes, the de-aluminum back field, and the n-type layer, and passivation with iodine, the silicon minority lifetime test is shown in FIGS. 7 and 8 .
Figure 7 Sample 1 minority son life test Figure 8 Sample 2 minority son life test
The silicon minority lifetime test has a good correspondence relationship with the LBIC current test and the battery EL test, which shows that the cause of the low battery efficiency is due to the internal defects of the silicon chip itself, which is not directly related to the battery process.
The silicon wafer was chemically polished and Wright liquid etched. Sample 2 exhibited a distinct pattern topography corresponding to the EL test, LBIC Current test, and minority lifetime test, as shown in Figure 9.
Figure 9 Pattern 2 after chemical etching
The optical microscopy of Specimen 1 is shown in Figures 10 and 11. The local area has a high dislocation density of about 10E5~10E6. The optical microscopy of sample 2 is shown in Figs. 12 and 13, and the dislocation density is as high as about 10E6 to 10E7 in the central circular pattern as shown in Fig. 9. The dislocation density in the edge area of ​​the black spot is more than 106/cm2, which is 1000 to 10000 times that of the dislocation-free single crystal, which is a considerable dislocation density.
Finally, the SIMS test was performed on the inside and outside of the black heart shown in the sample 2 in Figure 9, and the test results are shown in Table 2. SIMS test results showed that the content of various impurities inside and outside the black heart is normal.
Table 2 Sample 2 SIMS Test
3.0 Causes of Black Core or Black Spots
There are two main reasons that cause black spots or black spots on the cells: one is that the content of impurity ions is too high, and the other is that there are defects in the silicon wafer itself, that is, dislocations.
Dislocation can also be referred to as dislocation. In materials science, it refers to an internal microscopic defect of a crystalline material, namely a local irregular arrangement of atoms (crystallographic defects). From the geometric point of view, dislocations belong to a kind of line defect, which can be regarded as the boundary between the slipped part and the non-slip part in the crystal, and its presence has great influence on the physical properties of the material, especially the mechanical properties.
If there is a very high dislocation density in the silicon wafer, it becomes a strong recombination center for minority carriers, which leads to a short lifetime of the minority carrier and eventually leads to a serious drop in battery performance.
In summary, the black chip will reduce the power of the component, the hot spot effect is serious, and the life of the component is greatly reduced. (The author WeChat public account: Photovoltaic experience network)
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